This application claims the benefit of Korean Application No. 2001-81446, filed Dec. 19, 2001, in the Korean Industrial Property Office, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a thin film transistor using metal induced lateral crystallization (hereinafter referred to as xe2x80x9cMILCxe2x80x9d) and a method of fabricating the same, and more particularly, to a TFT with multiple gates which prevents defects by removing MILC surfaces in a channel region and reduces leakage current by materializing multiple gates without increasing the area, and a method of fabricating the same.
2. Description of Related Art
A polysilicon film which is used as a semiconductor layer of a TFT is formed by crystallizing the deposited amorphous silicon film after depositing an amorphous silicon film on a substrate. Methods of crystallizing the amorphous silicon film into a polysilicon film include solid phase crystallization (SPC), eximer laser annealing (ELA), metal induced lateral crystallization (MILC), etc. The SPC process has problems of a high crystallization temperature and a long period of process time while the ELA process has problems of time and space non-uniformities due to instability of a laser. Although the MILC process has merits of a relatively low process temperature and short process time using ordinary heat treatment equipment, it has problems in that a leakage current of a device fabricated by the MILC process is larger than that of a device fabricated by other crystallization methods.
A method of fabricating a TFT using the MILC process is disclosed in U.S. Pat. No. 5,773,327. The method of fabricating a TFT suggested in U.S. Pat. No. 5,773,327 requires an additional mask process to form an MILC region, and the existence of MILC surfaces in the channel region act as defects of the TFT. The MILC surface refers to a portion in which two surfaces of crystallized polysilicon grown in an opposite direction by the MILC technique meet.
On the other hand, there are problems in that a crystallization time is increased since dimensions by multiple gates are increased, and dimensions separated between metal layers of the MILC are increased in the case that multiple gates are applied to control leakage current.
Accordingly, it is an object of the present invention to provide a TFT which is capable of realizing multiple gates without increasing dimensions thereof, and a method of fabricating the same.
It is another object of the present invention to provide a TFT with multiple gates which are capable of reducing leakage current, and a method of fabricating the same.
It is another object of the present invention to provide a TFT with multiple gates using each of separated multi-channel layers, and a method of fabricating the same.
It is another object of the present invention to provide a TFT with multiple gates using an MILC process in which the MILC surface exists outside a channel layer, and a method of fabricating the same.
It is another object of the present invention to provide a method of fabricating a TFT with multiple gates using an MILC process which is capable of reducing the masking process.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
The foregoing and other objects of the present invention may be achieved by providing a thin film transistor using an MILC process comprising: a semiconductor layer which is formed on a insulating substrate in a zigzag shape; and a gate electrode which is formed so that it intersects with the semiconductor layer, wherein the semiconductor layer has an MILC surface at a part which is not crossed by the gate electrode.
The semiconductor layer comprises: two or more body parts intersecting with the gate electrode; and one or more connection parts to connect each neighboring body part, and wherein a part intersecting with the gate electrode in the semiconductor layer acts as a channel region.
The gate electrode is equipped with one or more slots intersecting the semiconductor layer, wherein a part overlapped with the channel region of the semiconductor layer acts as a multiple gate.
The foregoing and other objects of the present invention may also be achieved by providing a thin film transistor using an MILC process comprising: multi-semiconductor layers each of which is adjacently formed on a insulating substrate; and a gate electrode equipped with one or more slots intersecting with the multi-semiconductor layers, wherein MILC surfaces do not exist in the multi-semiconductor layers.
The foregoing and other objects of the present invention may also be achieved by providing a method of fabricating a thin film transistor with multiple gates using an MILC process comprising: forming an amorphous silicon film in a zigzag shape on a insulating substrate; forming a gate insulating film on the front surface of the substrate; forming a gate electrode on a gate insulating film so that the gate electrode intersects with an amorphous silicon film; forming on the front surface of the substrate an interlayer insulating film equipped with contact holes exposing edges of each of two sides of the amorphous silicon film; forming a metal layer contacting the exposed part of the amorphous silicon film through the contact holes; forming a semiconductor layer comprising a polycrystalline silicon film by crystallizing the amorphous silicon film using the MILC process; and forming source/drain electrodes contacting the semiconductor layers through the contact holes.
The foregoing and other objects of the present invention may also be achieved by providing a method of fabricating a thin film transistor with multiple gates using an MILC process comprising: forming a multi-semiconductor layer having neighboring polycrstalline silicon films using the MILC process on an insulating substrate; forming a gate electrode equipped with one or more slots intersecting with the multi-semiconductor layer; forming contact holes so that each of two edges of the multi-semiconductor layer are exposed; simultaneously forming source/drain electrodes contacting one exposed side edge of the multi-semiconductor layer, and forming a link to connect the other exposed side edge of the multi-semiconductor layer with a multi-semiconductor layer to be contacted.